1. Field of the Invention
This invention relates to an IC packing device for packing a semiconductor device in an IC or LSI unit by means of a film carrier.
2. Description of the Related Art
With the current progress of technology of manufacturing integrated circuits including IC and LSIs, the number of electrode pads to be arranged on a semiconductor device has been inevitably and remarkably increased in order to accommodate a large number of wires including those for power supply lines, input signal lines and other lines and, at the same time, the level of power consumption has risen considerably, and such a semiconductor device may operate at a very high speed. Wires arranged in a so-called packaged apparatus and terminals of a semiconductor device loaded in an apparatus of this type are normally connected by means of so-called bonding wires. However, as the level of integration of ICs and LSIs is raised and hence bonding pads are arranged very densely, there arise problems including the following.
1) The movement of the tool being used for a bonding operation can be blocked by nearby wires so as to obstruct the operation.
2) As there exists a bottom line for the size and pitch of arrangement of bonding pads that limits the miniaturization of bonding pads, the dimensions of a semiconductor device cannot be infinitely reduced. Consequently, there also exits a bottom line for the length of signal carrying wires to be arranged on a semiconductor device.
A technique called TAB (Tape Automated Bonding) has been proposed in an attempt to avoid these problems. With TAB, metal wires are arranged on a relatively long substrate made of flexible resin film and these wire are connected with respective matching input electrode pads of semiconductor devices mounted on the substrate by means of salient electrodes called bumps. Devices having a large number of input/output electrode pads as well as devices such as GaAs ICs that meet the requirement of high speed operation can be manufactured by using the TAB technique. Some of the known TAB-related methods and devices are disclosed in K. Furukawa et al., Japanese Patent No. 2-121342; Oct. 8, 1988), Y. Kondo et al.; Japanese Patent No. 2-121344; May 9, 1990) and C. Takubo et al.; U.S. Pat. No. 4,991,001; Feb. 5, 1991.
FIGS. 1A and 1B of the accompanying drawings show a film carrier to be used with a known TAB method and a semiconductor device mounted on the film carrier.
Referring to FIGS. 1A and 1B, a strip of resin film 20 (hereinafter referred to as "film") to be used for a film carrier has perforations 13 arranged along its lateral edges at a given pitch. Openings 2 for receiving semiconductor devices 1 are formed along the center of the film 20. Four isogonal-trapezoidal openings 4 are symmetrically arranged along the edges of a semiconductor device receiving opening 2 to surround the latter and spaced apart by a given distance from the respective corresponding edges of the opening 2. Each of the openings 4 is separated from the adjacent ones by film bridges 14, the number of which is four in total for an opening 2. Wires 6 are mainly laid on a film area 3 defined by the openings 2 and 4. Each of the wires 6 is provided with an outer lead 7 at an end that acts as a terminal for connection with an external element and an inner lead 5 at the other end.
When viewed from a side (see FIG. 1B), each of the wires 6 of a semiconductor unit having a configuration as described above is bent downward at its inner lead portion 5 at the time of manufacturing because of a low profile of the corresponding electrode pad of the semiconductor device 1. The downward bending of the inner leads 5 of a semiconductor unit is done to avoid short circuiting that can take place when one of the leads touches an edge of the semiconductor device 1 if the electrode pads of the semiconductor device 1 stand higher than the wires on the film. Therefore, the top of each electrode pad of a semiconductor device 1 is made lower than the corresponding wire 6 laid on a film. However, since the difference in height between the top of an electrode pad and a corresponding wire can vary as a function of, among other things, the thickness of the adhesive applied there and that of the semiconductor device mounted there if the bottom of the semiconductor device is grounded to reduce the overall thickness, it is quite possible that it becomes greater than an intended value. Then, any of the inner leads 5 of a semiconductor unit can be severely bent and eventually broken. The possibility of broken inner leads is particularly high when a large number of pins are used for a semiconductor device because inner leads should be arranged at a high pitch around the semiconductor device and, therefore, they should be made very narrow and thin, significantly reducing their mechanical strength. The probability of broken inner leads may be somewhat reduced if they are made relatively long. In order to prevent broken inner leads in a production process, the length of inner leads apparently has a maximum limit. Besides, longer inner leads result in an enhanced inductance and deterioration of the quality of high speed signals.
As is described above, for an LSI to achieve an enhanced level of integration, the number of pins to be used for each semiconductor device should be increased. To meet this requirement, the pitch of arrangement of inner leads of a semiconductor device needs to be reduced, requiring by the use of narrow and thin inner leads which partly lose their strength, leading to an increased probability of broken inner leads at the time of bending operation.
Additionally, as the level of integration of an LSI is enhanced, it can emit more heat, which should be effectively removed from the LSI or, more particularly, from the semiconductor device it comprises.